Advancing AI and HPC Chip Design: In a groundbreaking achievement, Synopsys Inc., a powerhouse in electronic design automation, has announced the validation of its AI-focused digital and analog design flows within Samsung Foundry’s cutting-edge SF2 process. This move follows a series of successful test chips, marking both digital and analog design flows as production-ready for this advanced process.
Through collaboration with Samsung Electronics, significant enhancements have been realized in performance, power, and area optimization (PPA) for Samsung’s sophisticated Gate-All-Around (GAA) process technologies. By utilizing Synopsys’s design technology co-optimization (DTCO) solutions, the SF2 process showed an impressive performance increase of 12%, a reduction in power consumption by 25%, and a 5% decrease in chip area compared to base designs without AI optimization.
Pushing the Envelope in Semiconductor Design: Sanjay Bali, Vice President of Product Management and Strategy at Synopsys, emphasized the importance of ecosystem collaboration in meeting the design requirements for SoC’s dedicated to the era of pervasive intelligence. Certified design flows and proven Synopsys intellectual property (IP) offer designers a dependable path to achieve aggressive targets and accelerate market entry.
Sangyun Kim, Vice President and Head of the Foundry Design Technology Team at Samsung Electronics, endorsed the long-standing partnership with Synopsys and the shared goal of addressing the growing demands for high-performance computing capabilities in the industry.
The joint efforts have also resulted in a new analog design transition reference flow, which simplifies the transition of Samsung’s 8nm analog IPs to the SF2 process. Innovative design techniques such as backend routing and nanosheet cell design for the SF2Z process technology further advanced the achievements, achieving up to 20% reduction in area.
Leveraging Synopsys IP Portfolio for Competitive Edge: With a comprehensive IP portfolio ranging from standard to automotive-grade for Samsung’s processes, Synopsys aims to provide chip manufacturers with a competitive edge by minimizing integration risks. Additionally, Synopsys’s 3DIC Compiler has been qualified for the SF2 process, facilitating multi-die designs from planning to sign-off, supporting Samsung’s advanced silicon processes and packaging technologies.
These developments underscore the ongoing commitment of Synopsys and Samsung to drive the semiconductor industry forward through AI-focused innovation and collaboration. As Synopsys continues to innovate in the semiconductor realm, its financials reflect a company of noteworthy strength, boasting an impressive market valuation and striking gross profit margins according to InvestingPro data.
The collaboration between Synopsys and Samsung is a significant step in advancing AI and high-performance computing (HPC) chip design. Here are some additional relevant details and discussion points that were not mentioned in the article:
Industry Context:
The semiconductor industry is seeing a rising demand for chips with better performance, power efficiency, and area optimization, mainly due to the proliferation of AI and HPC applications across various industries, including self-driving cars, cloud computing, and mobile devices. Synopsys and Samsung’s achievement addresses this demand by delivering more efficient and powerful chip designs.
Technological Background:
Synopsics is known for its electronic design automation (EDA) software and IP products, which are essential tools for developing sophisticated semiconductors. Samsung’s SF2 process utilizing Gate-All-Around (GAA) technology is a next-generation transistor architecture that allows for further scaling down of chip components, improving performance and power efficiency over the conventional FinFET process.
Key Challenges and Controversies:
A significant challenge in semiconductor design is the constant pressure to follow Moore’s Law, which predicts that the number of transistors on a microchip doubles about every two years, though maintaining this pace has become increasingly difficult. There is also the ongoing global semiconductor shortage, making it crucial for industry leaders like Samsung and Synopsys to innovate and improve their manufacturing and design processes to meet demand.
Advantages and Disadvantages:
Advantages of the collaboration include:
– Achievement of significant improvements in PPA, crucial for energy-efficient and high-performance AI chips.
– Enhanced competitiveness for chip manufacturers, through readily available certified design flows and IP.
– Facilitation of 3DIC designs promotes system-level innovation in multi-die integration.
Disadvantages may include:
– Potential increases in design and manufacturing complexity.
– The rate of technological advancements might result in shortened product life cycles and a faster pace of obsolescence.
– Small and medium-sized enterprises (SMEs) might face challenges in keeping up with the rapid advancements due to the high costs of utilizing cutting-edge technologies like SF2.
As for references and further information, interested individuals can visit the main domains of Synopsys and Samsung. Here are the links:
It’s important to note that for the most recent and in-depth information regarding their collaboration, progress, and specific technologies employed, the respective company’s official press releases, investor relations sections, or dedicated news pages would be the best sources.